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Flip Flops MC100E131FNR2G
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MC100E131FNR2G
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| HTS | 8542330001 |
| PPAP | No |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Inverting/Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 28 |
| Set/Reset | Set/Reset |
| Automotive | No |
| Lead Shape | J-Lead |
| PCB changed | 28 |
| Part Status | Active |
| Logic Family | ECL |
| Package Width | 11.58(Max) |
| Logic Function | D-Master-Slave Type |
| Package Height | 3.69(Min) |
| Package Length | 11.58(Max) |
| Triggering Type | Positive-Edge |
| Supplier Package | PLCC |
| Input Signal Type | Single-Ended |
| Process Technology | ECL |
| Standard Package Name | LCC |
| Number of Element Inputs | 4 |
| Number of Element Outputs | 4 |
| Number of Channels per Chip | 4 |
| Number of Elements per Chip | 1 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | 0 |
| Absolute Propagation Delay Time (ns) | 0.875 |
| Maximum Operating Supply Voltage (V) | 5.7|-5.7 |
| Minimum Operating Supply Voltage (V) | -4.2|4.2 |
| Typical Operating Supply Voltage (V) | -5|5 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 0.675@5V |
| Description |
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