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74LVT74PW,112
74LVT74PW,112
Flip Flops 74LVT74PW,112
NXP
74LVT74PW,112
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Standard and Specialty Logic
Flip Flops
Specification
Product AttributeAttribute Value
PPAPNo
EU RoHSCompliant
Bus HoldNo
MountingSurface Mount
PolarityInverting/Non-Inverting
ECCN (US)EAR99
PackagingBulk
Pin Count14
Set/ResetSet/Reset
AutomotiveNo
PCB changed14
Part StatusObsolete
Logic FamilyLVT
Package Width4.5(Max)
Logic FunctionD-Type
Package Height0.95(Max)
Package Length5.1(Max)
Triggering TypePositive-Edge
Supplier PackageTSSOP
Input Signal TypeSingle-Ended
Process TechnologyBiCMOS
Number of Element Inputs1
Number of Element Outputs1
Number of Channels per Chip2
Number of Elements per Chip2
Maximum Quiescent Current (mA)0.5(Typ)
Maximum Operating Temperature (°C)85
Minimum Operating Temperature (°C)-40
Absolute Propagation Delay Time (ns)6.2
Maximum Operating Supply Voltage (V)3.6
Minimum Operating Supply Voltage (V)2.7
Typical Operating Supply Voltage (V)3.3
Maximum Low Level Output Current (mA)32
Propagation Delay Test Condition (pF)50
Maximum High Level Output Current (mA)-20
Maximum Propagation Delay Time @ Maximum CL (ns)3.6(Typ)@3.3V
Description
Flip Flop D-Type Pos-Edge 2-Element 14-Pin TSSOP Bulk
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