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74LVC109D
74LVC109D
Flip Flops 74LVC109D
Nexperia
74LVC109D
--
Standard and Specialty Logic
Flip Flops
74LVC109D.pdf
Specification
Product AttributeAttribute Value
PPAPNo
EU RoHSSupplier Unconfirmed
Bus HoldNo
MountingSurface Mount
PolarityInverting/Non-Inverting
ECCN (US)EAR99
Pin Count16
Set/ResetSet/Reset
AutomotiveNo
PCB changed16
Part StatusObsolete
Logic FamilyLVC
Package Width4(Max)
Logic FunctionJK# -Type
Package Height1.45(Max)
Package Length10(Max)
Triggering TypePositive-Edge
Supplier PackageSO
Input Signal TypeSingle-Ended
Process TechnologyCMOS
Number of Element Inputs2
Number of Element Outputs1
Number of Channels per Chip2
Number of Elements per Chip2
Maximum Quiescent Current (mA)0.0001(Typ)
Maximum Operating Temperature (°C)125
Minimum Operating Temperature (°C)-40
Absolute Propagation Delay Time (ns)18
Maximum Operating Supply Voltage (V)3.6
Minimum Operating Supply Voltage (V)1.2
Typical Operating Supply Voltage (V)1.8|2.5|3.3
Maximum Low Level Output Current (mA)24
Propagation Delay Test Condition (pF)50
Maximum High Level Output Current (mA)-24
Maximum Propagation Delay Time @ Maximum CL (ns)3.9(Typ)@2.7V|3.5(Typ)@3.3V
Description
Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin SO
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