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Flip Flops 74LV74PW-Q100J
Nexperia
74LV74PW-Q100J
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| PPAP | Unknown |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Inverting/Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 14 |
| Set/Reset | Set/Reset |
| Automotive | Yes |
| PCB changed | 14 |
| Part Status | Active |
| Logic Family | LV |
| Package Width | 4.5(Max) |
| Logic Function | D-Type |
| Package Height | 0.95(Max) |
| Package Length | 5.1(Max) |
| Triggering Type | Positive-Edge |
| Supplier Package | TSSOP |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Number of Element Inputs | 1 |
| Number of Element Outputs | 1 |
| Number of Channels per Chip | 2 |
| Number of Elements per Chip | 2 |
| Maximum Quiescent Current (mA) | 0.08 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 58 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Minimum Operating Supply Voltage (V) | 1 |
| Typical Operating Supply Voltage (V) | 3.3 |
| Maximum Low Level Output Current (mA) | 12 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -12 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 70(Typ)@1.2V|24(Typ)@2V|18(Typ)@2.7V|13(Typ)@3.3V|9.5(Typ)@5V |
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