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Counter Shift Registers 74LV4020PW,112
NXP
74LV4020PW,112
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Standard and Specialty Logic
Counter Shift Registers
Specification
| Product Attribute | Attribute Value |
| PPAP | Unknown |
| Type | Binary |
| EU RoHS | Supplier Unconfirmed |
| Mounting | Surface Mount |
| ECCN (US) | EAR99 |
| Packaging | Bulk |
| Pin Count | 16 |
| Automotive | Unknown |
| Reset Type | Asynchronous |
| PCB changed | 16 |
| Part Status | Obsolete |
| Logic Family | LV |
| Package Width | 4.5(Max) |
| Direction Type | Uni-Directional |
| Logic Function | Counter |
| Operation Mode | UP Counter |
| Package Height | 0.95(Max) |
| Package Length | 5.1(Max) |
| Triggering Type | Negative-Edge |
| Number of Stages | 14 |
| Supplier Package | TSSOP |
| Process Technology | CMOS |
| Parallel Enable Input | No |
| Standard Package Name | SOP |
| Terminal Count Output | No |
| Number of Element Inputs | 1 |
| Number of Element Outputs | 12 |
| Number of Elements per Chip | 1 |
| Number of Count Input Enables | 0 |
| Maximum Quiescent Current (mA) | 0.16 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 55 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Minimum Operating Supply Voltage (V) | 1 |
| Typical Operating Supply Voltage (V) | 3.3 |
| Propagation Delay Test Condition (pF) | 50 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 60(Typ)@1.2V|27(Typ)@2V|19(Typ)@2.7V|16(Typ)@3V to 3.6V|11(Typ)@4.5V to 5.5V |
| Description |
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