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Bus Transceivers 74ALVCH16652DGG:11
NXP
74ALVCH16652DGG:11
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Transceivers
Bus Transceivers
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Compliant |
| Bus Hold | Yes |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Pin Count | 56 |
| Automotive | No |
| Input Level | LVTTL |
| Output Type | 3-State |
| PCB changed | 56 |
| Part Status | Obsolete |
| Logic Family | ALVC |
| Output Level | LVTTL |
| Package Width | 6.2(Max) |
| Logic Function | Bus Transceiver/Register |
| Package Height | 1.05(Max) |
| Package Length | 14.1(Max) |
| Triggering Type | Positive-Edge |
| Supplier Package | TSSOP |
| Process Technology | CMOS |
| Data Flow Direction | Bi-Directional |
| Number of Channels per Chip | 16 |
| Number of Elements per Chip | 2 |
| Maximum Power Dissipation (mW) | 600 |
| Maximum Quiescent Current (uA) | 40 |
| Typical Quiescent Current (uA) | 0.2 |
| Number of Direction Control Inputs | 0 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -40 |
| Number of Input Enables per Element | 0 |
| Absolute Propagation Delay Time (ns) | 6.8 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 1.2 |
| Number of Output Enables per Element | 1 Low/1 High |
| Maximum Low Level Output Current (mA) | 24 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -24 |
| Number of Selection Inputs per Element | 2 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 2.9(Typ)@3.3V|3.1(Typ)@2.7V |
| Description |
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