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Buffers and Line Drivers 74AUP2G240DC,125
Nexperia
74AUP2G240DC,125
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Standard and Specialty Logic
Buffers and Line Drivers
Specification
| Product Attribute | Attribute Value |
| PPAP | Unknown |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 8 |
| Automotive | Unknown |
| Output Type | 3-State |
| PCB changed | 8 |
| Part Status | Active |
| Logic Family | AUP |
| Package Width | 2.4(Max) |
| Logic Function | Buffer/Line Driver |
| Package Height | 0.85(Max) |
| Package Length | 2.1(Max) |
| Supplier Package | VSSOP |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Number of Inputs per Chip | 2 |
| Number of Outputs per Chip | 2 |
| Number of Channels per Chip | 2 |
| Number of Elements per Chip | 2 |
| Maximum Power Dissipation (mW) | 250 |
| Maximum Quiescent Current (uA) | 0.5 |
| Number of Input Enables per Chip | 0 |
| Number of Output Enables per Chip | 2 Low |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 29.5 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 0.8 |
| Typical Operating Supply Voltage (V) | 3.3|1.8|2.5 |
| Maximum Low Level Output Current (mA) | 4 |
| Propagation Delay Test Condition (pF) | 30 |
| Maximum High Level Output Current (mA) | -4 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 6.4@3V to 3.6V|7.1@2.3V to 2.7V|21.6@1.1V to 1.3V|12.3@1.4V to 1.6V|9.5@1.65V to 1.95V |
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